|
|
||
|
|
Program for 2008 (subject to change)
Sunday, October 26, 2008
Mezzanine 12:00 -5:00 pm Registration for FDIP and EPEP Conference
California Ballroom H-J 1:15 5:55 pm FDIP Workshop
MONDAY, OCTOBER 27, 2008
Mezzanine7:00 - 8:00 am Registration
Mezzanine7:00 - 8:00 am Continental Breakfast
California Ballroom H-M8:00 - 8:10 am Welcome/Introductory RemarksMichael Lamson
8:10-8:40 Session I Plenary/Keynote KEYNOTE: Ted Vucurevich Cadence Design Systems
8:40 10:00 am Session II Power Integrity I Session Chairs: Brian Young , Texas Instruments Tawfik Rehal-Arabi, Intel
Architecture Constraints over Dynamic Current Consumption Gilad Yahalom, Omer Vikinski and Gregory Sizikov............................................ Intel Corp
Verification and Co-Design of the Package and Die Power Delivery System Using Wavelets Imad A. Ferzli.................................................................................... University of Toronto Eli Chiprout......................................................................................................... Intel Corp Farid N. Najm................................................................................... University of Toronto
3D Power Distribution Network Co-design for Nanoscale Stacked Silicon IC Amirali Shayan, Xiang Hu, He Peng, Wanping Zhang and Chung-Kuan Cheng....................................................... University of California San Diego Mikhail Popovich and Xiaoming Chen................................................................ Qualcomm
Designs of Signal-Ground Bump-Patterns for Minimizing the Simultaneous Switching Noise in a Ball Grid Array Ruey-Bo Sun............................................................................. National Taiwan University Chien-Min Lin......................................................................................................... TSMC Ruey-Beei Wu........................................................................... National Taiwan University
San Jose Ballroom10:00 10:15 am Refreshment Break
California Ballroom H-M Tutorial I Session Chair: Ram Achar, Carleton University
An End-to-End Multi-GHz Serial Channel Design Process Douglas B. White, Chong Ding, Stephen A. Scearce, Divya Gopinath and Robert J. Evans............................................................................................ Cisco Systems
10:15 11:00 am
11:00 12:40 Session III High Speed Link Session Chairs: Moises Cases, IBM Robert Evans, Cisco Systems
Design and Analysis of a TB/sec Memory System Wendemagegnehu T. Beyene, Chris Madden, Namhoon Kim, Hae-Chang Lee Rich Perego, Dave Secker, Chuck Yuan, Arun Vaidyanath and Ken Chang............ Rambus
Statistical Link Analysis of High-Speed Memory I/O Interfaces during Simultaneous Switching Events Jihong Ren, Dan Oh, Sam Chang and Frank Lambrecht ......................................... Rambus
Pseudo-Differential Signaling Scheme Based on 4b/6b Multiwire Code Dan Oh, Fred Ware, WooPoung Kim, Joong-Ho Kim, John Wilson, Lei Luo, Jade Kizer, Ralf Schmitt, Chuck Yuan and John Eble...............................................Rambus
On-Chip Bus Signaling Using Passive Compensation Yulei Zhang and Ling Zhang............................................ University of California, San Diego Alina Deutsch, George Katopis and Daniel Dreps........................................................ IBM James Buckwalter.......................................................... University of California, San Diego Ernest Kuh....................................................................... University of California, Berkeley Chung-Kuan Cheng........................................................ University of California, San Diego
An Active Crosstalk Reduction Technique for Parallel High-Speed links in Low Cost Wirebond BGA Packages Yan Hu, Jikai Chen.............................................................................. University of Florida Michael Lamson......................................................................... Texas Instruments (retired) Rizwan Bashirullah............................................................................... University of Florida
California Ballroom C-G 12:40 1:40 Lunch (for conference attendees)
California Ballroom H-M 1:40 3:20 Session IV Signal Integrity I Session Chairs: Dale Becker, IBM Dan Oh, Rambus
SSN Mitigation By Means of a 2D EBG Structure with Square Patches and Meander Lines A. Ciccomancini Scogna............................................................................ CST of America
Compact Expressions for Period Jitter of Global Binary Clock Trees Jinwook Jang............................................................................ University of Massachusetts Olivier Franza........................................................................................... Intel Corporation Wayne Burleson....................................................................... University of Massachusetts
Multimode Signaling on Non-Ideal Channels Yongjin Choi, Chanyoun Won and Paul D. Franzon............. North Carolina State University Henning Braunisch and Kemal Aygόn........................................................ Intel Corporation
CMOS Circuit Simulation Using Latency Insertion Method Tadatoshi Sekine and Hideki Asai......................................................... Shizuoka University
Chip-Package Co-Design Methodology for Global Co-Simulation of Re-Distribution Layers (RDL) Sidina Wane.................................................................................. NXP-Semiconductors 2 An-Yu Kuo.................................................................................. Apache Design Solutions San Jose Ballroom 3:20 -3:35 pm Refreshment Break
California Ballroom H-M 3:35 4:55 pm Session V Measurement Session Chairs: Kathleen Melde, University of Arizona Ramesh Abhari, McGill University
On-chip Oscilloscope for Signal Integrity Characterization of Interconnects in 130nm CMOS Technology Pavle Milosevic and Josι E. Schutt-Ainι................. University of Illinois Urbana-Champaign
Measurement Techniques for On-chip Power Supply Noise Waveforms based on Fluctuated Sampling Delays in Inverter Chain Circuits Yutaka Uematsu, Hideki Osaka, Eiichi Suzuki, Masayoshi Yagyu and Tatsuya Saito........................................................................................................... Hitachi
Correlation of PDN Impedance with Jitter and Voltage Margin for High Speed Channels Vishal Laddha and Madhavan Swaminathan......................... Georgia Institute of Technology
Accurate Resistance, Inductance, Capacitance, and Conductance (RLCG) from Uniform Transmission Line Measurements M. J. Degerstrom, B. K. Gilbert and E. S. Daniel................................................................ .............................................. Mayo Clinic Special Purpose Processor Development Group
San Jose Ballroom
4:55 6:30 pm Session VI - Open Forum (Posters)
Design, Modeling, and Characterization of Embedded Electromagnetic Band Gap (EBG) Structure Suzanne Huh and Madhavan Swaminathan........................... Georgia Institute of Technology Fidel Muradali................................................................................ National Semiconductor
Simulation of Worst Case Switching Noise on a DDR2 Interface Rohan Mandrekar, Paul M Harvey, Jim Kuruts, Daniel Dreps, Tolga Ozguner, Yaping Zhou, Kazushige Kawasaki, Gary Lafontant and Gen Yamada......................... IBM
Placement of Shorting Vias for Power Integrity in Multi-Layered Structures Ssu-Hsuan Hsu, Yung-Shou Cheng and Wei-Da Guo................. National Taiwan University Hung-Hsiang Cheng and Chen-Chao Wang............... Advanced Semiconductor Engineering Ruey-Beei Wu........................................................................... National Taiwan University
Efficient Analysis for Multilayer Power-Ground Planes with Multiple Vias and Signal Traces in an Advanced Electronic Package Zaw Oo Zaw, Xing Chang Wei, En-Xiao Liu and Er-Ping Li ............................................................. A*STAR Institute of High Performance Computing Le-Wei Li......................................................................... National University of Singapore
Analysis of Entire Power Distribution System of Chip, Package and Board for High Speed IO Design Hsing-Chou Hsu........................................................................... Azurewave Technologies Jack Lin.................................................................................................................... Sigrity
Discussing Impedance Distribution with Multiple Stimulating Sources in Power Distribution System Design and Simulation Zhen Mu...................................................................................... Cadence Design Systems
A Resonance-Free Power Delivery System Design Methodology Applying 3D Optimized Extended Adaptive Voltage Positioning Tao Xu and Brad Brim.............................................................................................. Sigrity
Analysis of EBG Structures using SPICE Models of Multiple Planes Naoki Kobayashi, Ken Morishita and Takashi Harada........................................................ ...................................................................................... NEC System Jisso Research Labs
Multi-GHZ Modeling and Characterization of On-Chip Power Delivery Network Vishram S. Pandit and Woong Hwan Ryu................................................. Intel Corporation
Accurate Parasitic Inductance Determination of a Ceramic Capacitor through 2-Port Measurements Koh Yamanaga ..................... Tokyo Institute of Technology and Murata Manufacturing Co Takashi Sato and Kazuya Masu............................................. Tokyo Institute of Technology
Correlation of On-Die Capacitance for Power Delivery Network Yi-Feng Liu, Brian Wang, Mingming Xu, , Xiaoping Liu, Jie Zhu Chen and Michael Desmith.......................................................................................................... Intel
Hierarchical and Adaptive Finite-Element Reduction-Recovery Method for Large-Scale Power and Signal Integrity Analysis of High-Speed IC and Packaging Structures Houle Gan, Qing He and Dan Jiao............................................................ Purdue University
A Novel Stopband-Enhanced EBG Planes Using an Embedded Slow-wave Structure in Low-cost RF-SiP Chia-Yuan Hsieh, Hao-Hsiang Chuang and Ting-Kuang Wang ................................................................................................. National Taiwan University Chen-Chao Wang, Hung-Hsiang Cheng, Yei-Shen Wu, Chi-Tsung Chiu and Chih-Pin Hung.......................................................... Advanced Semiconductor Engineering Tzong-Lin Wu........................................................................... National Taiwan University
Ultra Wideband Wireless Serial Data Communication at 10Gb/s in CMOS 90nm Sameera Siddiqui and Tad Kwasniewski................................................... Carleton University
Effective Resolution of Design Issues in Telecommunication Blade Systems Bhyrav Mutnury, Nam Pham and Moises Cases........................................................... IBM Daniel N. De Araujo................................................................................................. Ansoft
A Dual-Slope Signaling Scheme to Suppress Electromagnetic Interference (EMI) with Sustaining Eye Margin Changwook Yoon................................................................................................... KAIST Seungyong Baek, HyungRok Lee and Youchul Jeong...................................... Silicon Image Jongbae Park and Hyunjeong Park.......................................................................... KAIST Baegin Sung................................................................................................... Silicon Image Joungho Kim........................................................................................................... KAIST
Characterization of Halogen-Free Package Materials Using Cavity Resonators Kemal Aygun and Grace Hu......................................................................................... Intel
Development of a Cost-Reduced Package thru DOE Validation and Zero-Margin Design Concept Jackson Kong, Jimmy Huang, Wan Ching Quah and Teong Keat Beh........................... Intel
Forwarded Clock based Receiver Characterization Methodology for Statistical Full Link Analysis Tools Santanu Chaudhuri, Rick L. Booth, Jayson Strayer, Nasser Kurd and Michael Sandhinti......................................................................................................... Intel
Analysis of Noise Coupling from Printed Circuit Board to Shielding Enclosure Zhenwei Yu................................................. Missouri University of Science and Technology Xiaopeng Dong, Jason Mix and Kevin Slattery............................................................. Intel Jun Fan........................................................ Missouri University of Science and Technology
California Ballroom D 7:30 -9:00 pm TPC Committee Meeting/Dinner
TUESDAY, OCTOBER 28, 2008
Mezzanine 7:00 - 8:00 am Continental Breakfast California Ballroom H-M8:00 8:45 am Tutorial II Session Chair: Ram Achar, Carleton University
Power Integrity for I/O Interfaces Vishram S. Pandit, Myoung J. Choi and Woong Hwan Ryu......................... Intel Corporation
California Ballroom H-M 8:45-10:25 Session VII Power Integrity II Session Chairs: Christopher Pan, Qualcomm Greg Taylor, Intel
Effectiveness of On-Die Decoupling Capacitance in Improving Chip Performance Isaac Kantorovich and Chris Houghton......................................................................... Intel
An Adaptive On-chip ESR Controller Scheme in Power Distribution Network for Simultaneous Switching Noise Reduction Jongjoo Shim and Minchul Shin............................................................................... KAIST Hyungsoo Kim, Yongju Kim and Kunwoo Park.............................. HYNIX Semiconductor Jeonghyeon Cho and Joungho Kim ......................................................................... KAIST
Suppression of Vertical Coupling using Electromagnetic Band Gap Structures Nithya Sankaran, Suzanne Huh, Madhavan Swaminathan and Rao Tummala........................ ........................................................................................... Georgia Institute of Technology
Including the Impact of Connecting Vias in the Performance Metric Evaluation for Board-Level Optimization of Decoupling Capacitors Mosin Mondal.............................................................................. University of Washington Samuel Connor and Bruce Archambeault..................................................................... IBM Vikram Jandhyala......................................................................... University of Washington
Robust Iterative Finite Element Solver for Multi-terminal Power Distribution Network Resistance Extraction Martien Oppeneer........................................................ Eindhoven University of Technology Prasad Sumant and Andreas C. Cangellaris............. University of Illinois Urbana-Champaign
San Jose Ballroom10:25 - 10:40 am Refreshment Break
California Ballroom H-M 10:40 12:20 Session VIII - Macromodels Session Chairs: Flavio Canavero, Politecnico di Torino Dhamendra Saraswat
The Design of Continuous-Time Linear Equalizers Using Model Order Reduction Techniques Wendemagegnehu (Wendem) T. Beyene................................................................ Rambus
Parallel Algorithm for Analysis of High-Speed Interconnects D. Paul, N. M. Nakhla, R. Achar and M. S. Nakhla............................. Carleton University
Nonlinear Circuit Solver with Linear Interconnect Load Albert E. Ruehli and Jerry Hayes................................................................................ IBM
Compact Macromodeling of Electrically Long Interconnects A. Chinea, P. Triverio, and S. Grivet-Talocia....................................... Politecnico di Torino
Passivity Enforcement via Quadratic Programming for Element-by-Element Rational Function Approximation of Passive Network Matrices Se-Jung Moon and A.C. Cangellaris................... University of Illinois at Urbana-Champaign
California Ballroom C-G12:20 am - 1:45 pm Lunch (for Meeting attendees)
Monterey Room 12:20 - 1:45 Technical Program Committee Meeting (Committee Members only) California Ballroom H-M1:45 2:30 pm Special Session - SI Education Session Chair: Ram Achar, Carleton University
An Industry-Oriented Curriculum in the Design and Performance of Electrical Packaging and Interconnect Robert J. Evans and Stephen Scearce........................................................... Cisco Systems Minjhing Hsieh.................................................................................... Engineering Learning
San Jose Ballroom 2:30 3:00 pm Refreshment Break
California Ballroom H-M 3:00 4:20 pm Session IX Signal Integrity II Session Chairs: Chuck Yuan, Tambus Stefano Grivet-Talocia, Politecnico di Torino Sensitivity Computation of Interconnect Capacitances with respect to Geometric Parameters Yu Bi and K. van der Kolk................................................... Delft University of Technology D. Ioan......................................................................... Politechnica University of Bucharest N.P. van der Meijs............................................................... Delft University of Technology
An Analysis on Measurement Sensitivity of Short-Pulse Propagation Technique Using a Virtual Test Bench Zhen Zhou.......................................................................................... University of Arizona Alina Deutsch.............................................................................................................. IBM Kathleen L. Melde.............................................................................. University of Arizona George A. Katopis and Jason D. Morsey.................................................................... IBM
An Efficient Inductance Extraction Algorithm for 3-D Interconnects with Frequency Dependent Nonlinear Magnetic Materials Yang Yi, Vivek Sarin and Weiping Shi............................................. Texas A&M University
High Frequency Loss Characterization of FCPBGA Package Materials with Humidity and Temperature Variation Jean Audet and Nanju Na........................................................................................... IBM San Jose Ballroom Session X Open Forum (Posters)4:20 6:20 pm
A Simple Method of Generating Causal Broadband RLGC Models for CPW Transmission Lines with Surface Roughness Zhen Zhou and Kathleen L. Melde...................................................... University of Arizona
Fast Iterative Solution Algorithms for the Frequency-Domain Layered Finite-Element Based Analysis of Large-Scale On-Chip Interconnect Structures Feng Sheng and Dan Jiao......................................................................... Purdue University
Compact On-Chip Wire Models for the Clock Distribution of High-Speed I/O Interfaces Xiaoning Qi, Joong-Ho Kim, Ling Yang, Ralf Schmitt and Chuck Yuan................... Rambus
Parallel Full-Chip Transient Simulation at Transistor Level He Peng and Chung-Kuan Cheng................................... University of California, San Diego Khosro Rouz and Manjit Borah................................................................ Fastrack Design
Design-performance aspects of Glass Ceramic in comparison to Alumina Ceramic and Organic FCPBGA Packages for High Link Densities of High Speed SerDes Haitian Hu, Nanju Na, Franklin Baez and Gary Lafontant............................................. IBM
Eliminating Via-Plane Coupling Using Ground Vias for High-Speed Signal Transitions Songping Wu and Xin Chang....................... Missouri University of Science and Technology Christian Schuster............................................................ Hamburg Univerity of Technology Xiaoxiong Gu.............................................................................................................. IBM Jun Fan........................................................ Missouri University of Science and Technology
Transient Simulation of Lossy Interconnects using the Latency Insertion Method (LIM) Dmitri Klokotov and Josι Schutt-Ainι................ University of Illinois at Urbana-Champaign
Effects of Partially Broken HF Signal Return on Different Packaging Levels Thomas-Michael Winkel and Roland Frech......................................................................... ....................................................................... IBM Deutschland Research & Development Thomas Gneiting................................................................................................... AdMOS
On Addressing the Practical Issues in the Extraction of RLGC Parameters for Lossy Multiconductor Transmission Lines using S-parameter Models Madhusudanan K Sampath.......................................................... Advanced Micro Devices
Utilizing Low Loss Dielectric Material for High Performance DRAM Window-BGA Design Hung-Hsiang Cheng, Chih-Yi Huang, Chen-Chao Wang, Chi-Tsung Chiu and Chih-Pin Hung.......................................................... Advanced Semiconductor Engineering
Controlled Impedance Chip-to-Chip Interconnect Using Coplanar Wire Bond Structures Samuel Harkness, Jeffrey Meirhofer and Brock J. LaMeres.......... Montana State University
A Parameterized Model Order Reduction Technique for Efficient Solution of FEM Eigenvalue Problems Majid Ahmadloo and Anestis Dounavis.................................. University of Western Ontario
Fast Reduced-Order Finite-Element Modeling of Lossy Coupled Wires Using Lumped Impedance Elements Shih-Hao Lee and Jian-Ming Jin......................... University of Illinois at Urbana-Champaign
Thermal Modeling of On-Chip Interconnects and 3D Packaging Using EM Tools Lijun Jiang ................................................................................................................ IBM Seshadri Kolluri........................................................ University of California, Santa Barbara Barry J. Rubin, Howard Smith, Evan G. Colgan, Michael R. Scheuermann, Jamil A. Wakil, Alina Deutsch and Jason Gill................................................................ IBM
An H2-Matrix-Based Integral-Equation Solver of Linear-Complexity for Large-Scale Full-Wave Modeling of 3D Circuits Wenwen Chai and Dan Jiao..................................................................... Purdue University
Time-Domain Orthogonal Finite-Element Reduction-Recovery (OrFE-RR) Method for Fast and Accurate Broadband Simulation of Die-Package Interaction Duo Chen and Dan Jiao.......................................................................... Purdue University
Proximity Interconnect Technology Utilizing Transmission Line Coupling for Stacked VLSI Chips Daisuke Iguchi............................................................................................. Fuji Xerox Co. Yutaka Akiyama....................................................................................... Meisei University Tsuneo Ito............................................................................................... Excel Service Co. Kanji Otsuka............................................................................................ Meisei University
AC Coupled Backplane Communication Using Embedded Capacitor Bruce Su............................................................................. North Carolina State University Pravin Patel, Steve W. Hunter and Moises Cases......................................................... IBM Paul D. Franzon.................................................................. North Carolina State University
Computer Code for Fast Macromodeling of Large Multiport Systems Dirk Deschrijver........................................................................................ Ghent University Bjorn Gustavsen ........................................................................ SINTEF Energy Research Tom Dhaene.............................................................................................. Ghent University
An Over-12-Gbps On-Chip Transmission Line Interconnect with a Pre-Emphasis Technique in 90 nm CMOS Kazuya Miyashita, Takahiro Ishii, Hiroyuki Ito, Noboru Ishihara and Kazuya Masu........................................................................ Tokyo Institute of Technology
Signal Integrity Improvement in Transmission Lines Backed by an EBG Structure Jin Chen and Ramesh Abhari.................................................................... McGill University
WEDNESDAY, OCTOBER 29, 2008
Mezzanine7:00 - 8:00 am Continental Breakfast
California Ballroom H-M8:00 9:20 am Session XII Signal Integrity III\ Session Chairs: Vikram Jandhyal, Washington State University Ruey-Beei Wu, National Taiwan University
Minimizing Crosstalk Noise in Vias or Pins by Optimizing Signal Assignment in a High-Speed Differential Bus Yaping Zhou, Rohan Mandrekar, Tingdong Zhou, Sungjun Chun, Paul Harvey and Roger Weekly...................................................................................................... IBM
Impedance Design for Multi-layered Vias Xiaoxiong Gu, Albert E. Ruehli and Mark B. Ritter...................................................... IBM
Fewest Vias Design for Microstrip Guard Trace by Using Overlying Dielectric Yung-Shou Cheng and Wei-Da Guo........................................... National Taiwan University Guang-Hwa Shiue............................................................. Chung Yuan Christian University Hung-Hsiang Cheng and Chen-Chao Wang............... Advanced Semiconductor Engineering Ruey-Beei Wu........................................................................... National Taiwan University
Suppression of Power/Ground Noise Using Differential ViasRuiming Chen, Haining Wang and Ramesh Abhari..................................... McGill University
9:20 10:05 am | |
