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Final Program Future Directions in IC and Package Design Workshop (FDIP) October 26, 2008, San Jose, CA sponsored by:
organized by: CPMT Technical Committee on Electrical Design, Modeling, and Simulation (TC-EDMS) 1:15pm - 1:30 pm Welcome Remarks, Alina Deutsch, IBM Madhavan Swaminathan, GIT
SESSION I: SYSTEM DESIGN 1:30pm – 4:30 pm Session Chair: Paul D. Franzon, – North Carolina State University
1:30pm – 2:05pm Architecture Implications of 3D Integration Technology – Michael Ignatowski, IBM Corporation
2:05pm – 2:40pm Design Considerations for Highly Integrated 3D SiP for Mobile Applications – Joungho Kim, KAIST Korea
2:40pm – 3:15pm Design of Through-Silicon Vias and Vertical Shielding for 3D Integration - Ivan Ndip, Fraunhofer Institute for Reliability & Microintegration, IZM, Germany
3:15pm – 3:50pm Tb/s-Class Module-to-Module Optical Data Buses on Printed-Circuit Boards - Fuad Doany, IBM Corporation
3:50 – 4:30 pm - Refreshment Break
SESSION II: MODELING 4:30pm – 6:25 pm Session Chair: Albert E. Ruehli, IBM Corporation
4:30pm – 5:05pm Electromagnetic Solvers for Interconnect and Package Modeling – New Developments – Sadasiva M. Rao, Auburn University
5:05pm – 5:40pm Accelerated Parallelized Integral Equation Techniques for Packaged Microelectronics – Vikram Jandhyala, University of Washington
5:40pm – 6:15pm Benefits of Surface Integral Equation Modeling Leveraging Massively Parallel Advanced Techniques – Jason D. Morsey, IBM Corporation
6:15pm – 6:25 pm Closing Remarks, Madhavan Swaminathan, GIT, Alina Deutsch, IBM
Presentations will be posted on the IEEE CPMT Society web page at: http://www.ewh.ieee.org/soc/cpmt/tc12/
Workshop Chairs:
Alina Deutsch Madhavan Swaminathan IBM Watson Research Center Georgia Institute of Technology
Technical Program Committee:
Tawfik Arabi – Intel Oregon Mahadevan Iyer - IME, Singapore Andreas Cangellaris - U of Illinois George Katopis - IBM Poughkeepsie Moises Cases - IBM Austin Istvan Novak - SUN Chi-Shih Chang – Consultant Toshio Sudo - Toshiba, Japan Paul Franzon - North Carolina State U Gregory Taylor - Intel Oregon Hartmut Grabinski - U of Hanover, Germany Lewis Terman – IBM Watson Research Brian Young – Texas Instruments
Workshop will be held at the Wyndham Hotel, 1350 N. 1st Street, San Jose, California 95112, (408) 453-6200. The hotel is holding a block of rooms for participants at a special rate of $119.00 plus tax. Room reservations must be made by September 25, 2008 to guarantee this rate. After that time rooms will be on a space and rate available basis only. Be sure to mention that you are attending the Electrical Performance of Electronic Packaging conference. Rooms are limited so make your reservations early. Additional information can be obtained at www.epep.org
Additional information may be obtained from the workshop chairs:
Alina Deutsch Madhavan Swaminathan deutsch@ieee.org madhavan.swaminathan@ece.gatech.edu phone: (914) 945-2858 phone: (404) 894-3340 fax: (914) 945-2141 fax: (404) 894-9959
and the workshop administration:
epd@engr.arizona.edu phone: (520) 621-3054 fax: (520) 621-1443
Attendees interested in the workshop will be charged a $60.00 fee that will cover afternoon refreshments, digest of abstracts, and posting of the foils on the CPMT Society TC-EDMS web site. All attendees must register by September 12, 2008 using the EPEP’08 website at www.epep.org in order to assure that the workshop is being held. On-site registrants will be admitted depending on availability of seating.
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